Categories
Electrical Engineering

In this homework, you are going to design and implement an AES encryption core o

In this homework, you are going to design and implement an AES encryption core on your Xilinx
FPGA board. Please follow PLD_Lecture on AES to figure out about AES algorithms. The block
diagram of AES encryption core is shown in Figure 1.
Figure 1: AES Encryption Block.
In this assignment your AES core will be instantiated in your top module Verilog code. The input
and output of your TOP module is based on Figure 2.
Figure 2: TOP Module.
Inputs:
● CLK100MHZ
It is the system frequency.
● SW[0]
It is the reset of your project. You have the option to use it as the AES reset as well. When
SW[0] is off it means your design is in reset state and when it is on, your design is in normal
operation. (this is a low active reset). In your board, we assume that if the switch is down,
2
it is considered as off, and it is on when the position of switch is up. (similar assumption
is considered for all other switches)
● SW[1]
This input is the starting command for the AES core. When the SW[1] is 1 the core should
start to encrypt PLAIN_TEXT[127:0] based on the KEY[127:0]. Note that to start another
128-bit block encryption, SW[1] should get 0 and then get 1. You need to instantiate a
filter for SW[1] (similar to previous homeworks) and then detect the rising edge of this
starting signal (START input of your AES core). Accordingly, you can use the following
codes; first instantiating the Filter module as below:
Then to detect the rising edge of SW_CMD, copy this code in your project:
Now SW_EDGE is the start of your AES core.
● SW[3:2]
The output of your AES core, i.e., CIPHER_TEXT, is 128 bits. You should show this output
on eight 7-SEG of your board. As you know, the 128 bit signal consists of 32 hex-digit. So,
you do not have enough 7-SEG to show the output. Hence, when SW[3:2] is 0 the first 8
hex-digit is appeared on 7-SEG, and the second 8 hex-digit is shown when SW[3:2] is 1
and the third and fourth 8 hex-digit are shown when SW[3:2] is 2 and 3 respectively. To
clarify, please consider this numerical example:
reg[127:0] CIPHER_TEXT;
CIPHER_TEXT = 128’h29C3505F571420F6402299B31A02D73A;
In Figure 3, you can see what should be shown on 7-SEGs for this example (the MSB bits
are shown in the last row in this figure.)
Filter #(.wd(16), .n(65535), .bound(64000)) uut(.clk(CLK100MHZ)
,.data_in(SW[1]),.data_out(SW_CMD));
reg SW_CMD_back;
reg SW_EDGE;
always @(posedge CLK100MHZ)
begin
SW_CMD_back <= SW_CMD;
SW_EDGE RC[1] = 8’b00000001
Round 2 => RC[2] = 8’b00000010
Round 3 => RC[3] = 8’b00000100
Round 4 => RC[4] = 8’b00001000
Round 5 => RC[5] = 8’b00010000
Round 6 => RC[6] = 8’b00100000
Round 7 => RC[7] = 8’b01000000
Round 8 => RC[8] = 8’b10000000
Round 9 => RC[9] = 8’b00011011
Round 10 => RC[10] = 8’b00110110
In our example, the KEY is :
KEY [127:0] = 128’h5468617473206D79204B756E67204675;
32-bit LSB of KEY is 32’h67204675
byte 0 => 67
byte 1 => 20
byte 2 => 46
9
byte 3 => 75
byte 0 => s_byte => 85
byte 1 => s_byte => b7
byte 2 => s_byte => 5a
byte 3 => s_byte => 9d
g0 => b7 ^ 01 => b6
g1 => 5a
g2 => 9d
g3 => 85
g => 32’hb65a9d85
After calculating g, we should calculate the KEY for the next round. In Figure 9 the structure to
generate the next round key is presented. Note that KEY for each round is generated based on
the previous round KEY.
Figure 9: KEY_GENERATOR.
KEY[127:96] => 32’h54686174
KEY[95:64] => 32’h73206D79
KEY[63:32] => 32’h204B756E
KEY[31:0] => 32’h67204675
KEY is Key of round 0 and KEY_1 includes the value of the first round key.
KEY_1[127:96] => KEY[127:96] ^ g = 54686174 ^ b65a9d85 = E232FCF1
KEY_1[95:64] => KEY[95:64] ^ KEY_1[127:96] = 73206D79 ^ E232FCF1 = 91129188
KEY_1[63:32] => KEY[63:32] ^ KEY_1[95:64] = 204B756E ^ 91129188 = B159E4E6
KEY_1[31:0] => KEY[31:0] ^ KEY_1[63:32] = 67204675 ^ B159E4E6 = D679A293
KEY_1[127:0] = 128’hE232FCF191129188B159E4E6D679A293
R0_S_mat_shift[127:0] = 128’hba75f47a84a48d32e88d060e1b407d5d
Round_1 = KEY_1 ^ R0_S_mat_shift = 128’h5847088B15B61CBA59D4E2E8CD39DFCE;
10
e2 91 b1 d6
32 12 59 79
fc 91 e4 a2
f1 88 e6 93
XOR
ba 84 e8 1b
75 a4 8d 40
f4 8d 06 7d
7a 32 0e 5d
=
58 15 59 cd
47 b6 d4 39
08 1c e2 df
8b ba e8 ce
KEY_1 After MIX_COLUMN Round1
Figure 10: data after round1.
So, if you are able to finish these steps (1-5), the thing that you need is to make a loop in your
code to repeat steps 2-5 nine times. After that you have finished 9 rounds, the round 10 is the
same as previous steps but the only difference is that you should exclude the MIX_COLUMN
module in the round 10.

Categories
Electrical Engineering

In this homework, you are going to design and implement an AES encryption core o

In this homework, you are going to design and implement an AES encryption core on your Xilinx
FPGA board. Please follow PLD_Lecture on AES to figure out about AES algorithms. The block
diagram of AES encryption core is shown in Figure 1.
Figure 1: AES Encryption Block.
In this assignment your AES core will be instantiated in your top module Verilog code. The input
and output of your TOP module is based on Figure 2.
Figure 2: TOP Module.
Inputs:
● CLK100MHZ
It is the system frequency.
● SW[0]
It is the reset of your project. You have the option to use it as the AES reset as well. When
SW[0] is off it means your design is in reset state and when it is on, your design is in normal
operation. (this is a low active reset). In your board, we assume that if the switch is down,
2
it is considered as off, and it is on when the position of switch is up. (similar assumption
is considered for all other switches)
● SW[1]
This input is the starting command for the AES core. When the SW[1] is 1 the core should
start to encrypt PLAIN_TEXT[127:0] based on the KEY[127:0]. Note that to start another
128-bit block encryption, SW[1] should get 0 and then get 1. You need to instantiate a
filter for SW[1] (similar to previous homeworks) and then detect the rising edge of this
starting signal (START input of your AES core). Accordingly, you can use the following
codes; first instantiating the Filter module as below:
Then to detect the rising edge of SW_CMD, copy this code in your project:
Now SW_EDGE is the start of your AES core.
● SW[3:2]
The output of your AES core, i.e., CIPHER_TEXT, is 128 bits. You should show this output
on eight 7-SEG of your board. As you know, the 128 bit signal consists of 32 hex-digit. So,
you do not have enough 7-SEG to show the output. Hence, when SW[3:2] is 0 the first 8
hex-digit is appeared on 7-SEG, and the second 8 hex-digit is shown when SW[3:2] is 1
and the third and fourth 8 hex-digit are shown when SW[3:2] is 2 and 3 respectively. To
clarify, please consider this numerical example:
reg[127:0] CIPHER_TEXT;
CIPHER_TEXT = 128’h29C3505F571420F6402299B31A02D73A;
In Figure 3, you can see what should be shown on 7-SEGs for this example (the MSB bits
are shown in the last row in this figure.)
Filter #(.wd(16), .n(65535), .bound(64000)) uut(.clk(CLK100MHZ)
,.data_in(SW[1]),.data_out(SW_CMD));
reg SW_CMD_back;
reg SW_EDGE;
always @(posedge CLK100MHZ)
begin
SW_CMD_back <= SW_CMD;
SW_EDGE RC[1] = 8’b00000001
Round 2 => RC[2] = 8’b00000010
Round 3 => RC[3] = 8’b00000100
Round 4 => RC[4] = 8’b00001000
Round 5 => RC[5] = 8’b00010000
Round 6 => RC[6] = 8’b00100000
Round 7 => RC[7] = 8’b01000000
Round 8 => RC[8] = 8’b10000000
Round 9 => RC[9] = 8’b00011011
Round 10 => RC[10] = 8’b00110110
In our example, the KEY is :
KEY [127:0] = 128’h5468617473206D79204B756E67204675;
32-bit LSB of KEY is 32’h67204675
byte 0 => 67
byte 1 => 20
byte 2 => 46
9
byte 3 => 75
byte 0 => s_byte => 85
byte 1 => s_byte => b7
byte 2 => s_byte => 5a
byte 3 => s_byte => 9d
g0 => b7 ^ 01 => b6
g1 => 5a
g2 => 9d
g3 => 85
g => 32’hb65a9d85
After calculating g, we should calculate the KEY for the next round. In Figure 9 the structure to
generate the next round key is presented. Note that KEY for each round is generated based on
the previous round KEY.
Figure 9: KEY_GENERATOR.
KEY[127:96] => 32’h54686174
KEY[95:64] => 32’h73206D79
KEY[63:32] => 32’h204B756E
KEY[31:0] => 32’h67204675
KEY is Key of round 0 and KEY_1 includes the value of the first round key.
KEY_1[127:96] => KEY[127:96] ^ g = 54686174 ^ b65a9d85 = E232FCF1
KEY_1[95:64] => KEY[95:64] ^ KEY_1[127:96] = 73206D79 ^ E232FCF1 = 91129188
KEY_1[63:32] => KEY[63:32] ^ KEY_1[95:64] = 204B756E ^ 91129188 = B159E4E6
KEY_1[31:0] => KEY[31:0] ^ KEY_1[63:32] = 67204675 ^ B159E4E6 = D679A293
KEY_1[127:0] = 128’hE232FCF191129188B159E4E6D679A293
R0_S_mat_shift[127:0] = 128’hba75f47a84a48d32e88d060e1b407d5d
Round_1 = KEY_1 ^ R0_S_mat_shift = 128’h5847088B15B61CBA59D4E2E8CD39DFCE;
10
e2 91 b1 d6
32 12 59 79
fc 91 e4 a2
f1 88 e6 93
XOR
ba 84 e8 1b
75 a4 8d 40
f4 8d 06 7d
7a 32 0e 5d
=
58 15 59 cd
47 b6 d4 39
08 1c e2 df
8b ba e8 ce
KEY_1 After MIX_COLUMN Round1
Figure 10: data after round1.
So, if you are able to finish these steps (1-5), the thing that you need is to make a loop in your
code to repeat steps 2-5 nine times. After that you have finished 9 rounds, the round 10 is the
same as previous steps but the only difference is that you should exclude the MIX_COLUMN
module in the round 10.

Categories
Electrical Engineering

In this homework, you are going to design and implement an AES encryption core o

In this homework, you are going to design and implement an AES encryption core on your Xilinx
FPGA board. Please follow PLD_Lecture on AES to figure out about AES algorithms. The block
diagram of AES encryption core is shown in Figure 1.
Figure 1: AES Encryption Block.
In this assignment your AES core will be instantiated in your top module Verilog code. The input
and output of your TOP module is based on Figure 2.
Figure 2: TOP Module.
Inputs:
● CLK100MHZ
It is the system frequency.
● SW[0]
It is the reset of your project. You have the option to use it as the AES reset as well. When
SW[0] is off it means your design is in reset state and when it is on, your design is in normal
operation. (this is a low active reset). In your board, we assume that if the switch is down,
2
it is considered as off, and it is on when the position of switch is up. (similar assumption
is considered for all other switches)
● SW[1]
This input is the starting command for the AES core. When the SW[1] is 1 the core should
start to encrypt PLAIN_TEXT[127:0] based on the KEY[127:0]. Note that to start another
128-bit block encryption, SW[1] should get 0 and then get 1. You need to instantiate a
filter for SW[1] (similar to previous homeworks) and then detect the rising edge of this
starting signal (START input of your AES core). Accordingly, you can use the following
codes; first instantiating the Filter module as below:
Then to detect the rising edge of SW_CMD, copy this code in your project:
Now SW_EDGE is the start of your AES core.
● SW[3:2]
The output of your AES core, i.e., CIPHER_TEXT, is 128 bits. You should show this output
on eight 7-SEG of your board. As you know, the 128 bit signal consists of 32 hex-digit. So,
you do not have enough 7-SEG to show the output. Hence, when SW[3:2] is 0 the first 8
hex-digit is appeared on 7-SEG, and the second 8 hex-digit is shown when SW[3:2] is 1
and the third and fourth 8 hex-digit are shown when SW[3:2] is 2 and 3 respectively. To
clarify, please consider this numerical example:
reg[127:0] CIPHER_TEXT;
CIPHER_TEXT = 128’h29C3505F571420F6402299B31A02D73A;
In Figure 3, you can see what should be shown on 7-SEGs for this example (the MSB bits
are shown in the last row in this figure.)
Filter #(.wd(16), .n(65535), .bound(64000)) uut(.clk(CLK100MHZ)
,.data_in(SW[1]),.data_out(SW_CMD));
reg SW_CMD_back;
reg SW_EDGE;
always @(posedge CLK100MHZ)
begin
SW_CMD_back <= SW_CMD;
SW_EDGE RC[1] = 8’b00000001
Round 2 => RC[2] = 8’b00000010
Round 3 => RC[3] = 8’b00000100
Round 4 => RC[4] = 8’b00001000
Round 5 => RC[5] = 8’b00010000
Round 6 => RC[6] = 8’b00100000
Round 7 => RC[7] = 8’b01000000
Round 8 => RC[8] = 8’b10000000
Round 9 => RC[9] = 8’b00011011
Round 10 => RC[10] = 8’b00110110
In our example, the KEY is :
KEY [127:0] = 128’h5468617473206D79204B756E67204675;
32-bit LSB of KEY is 32’h67204675
byte 0 => 67
byte 1 => 20
byte 2 => 46
9
byte 3 => 75
byte 0 => s_byte => 85
byte 1 => s_byte => b7
byte 2 => s_byte => 5a
byte 3 => s_byte => 9d
g0 => b7 ^ 01 => b6
g1 => 5a
g2 => 9d
g3 => 85
g => 32’hb65a9d85
After calculating g, we should calculate the KEY for the next round. In Figure 9 the structure to
generate the next round key is presented. Note that KEY for each round is generated based on
the previous round KEY.
Figure 9: KEY_GENERATOR.
KEY[127:96] => 32’h54686174
KEY[95:64] => 32’h73206D79
KEY[63:32] => 32’h204B756E
KEY[31:0] => 32’h67204675
KEY is Key of round 0 and KEY_1 includes the value of the first round key.
KEY_1[127:96] => KEY[127:96] ^ g = 54686174 ^ b65a9d85 = E232FCF1
KEY_1[95:64] => KEY[95:64] ^ KEY_1[127:96] = 73206D79 ^ E232FCF1 = 91129188
KEY_1[63:32] => KEY[63:32] ^ KEY_1[95:64] = 204B756E ^ 91129188 = B159E4E6
KEY_1[31:0] => KEY[31:0] ^ KEY_1[63:32] = 67204675 ^ B159E4E6 = D679A293
KEY_1[127:0] = 128’hE232FCF191129188B159E4E6D679A293
R0_S_mat_shift[127:0] = 128’hba75f47a84a48d32e88d060e1b407d5d
Round_1 = KEY_1 ^ R0_S_mat_shift = 128’h5847088B15B61CBA59D4E2E8CD39DFCE;
10
e2 91 b1 d6
32 12 59 79
fc 91 e4 a2
f1 88 e6 93
XOR
ba 84 e8 1b
75 a4 8d 40
f4 8d 06 7d
7a 32 0e 5d
=
58 15 59 cd
47 b6 d4 39
08 1c e2 df
8b ba e8 ce
KEY_1 After MIX_COLUMN Round1
Figure 10: data after round1.
So, if you are able to finish these steps (1-5), the thing that you need is to make a loop in your
code to repeat steps 2-5 nine times. After that you have finished 9 rounds, the round 10 is the
same as previous steps but the only difference is that you should exclude the MIX_COLUMN
module in the round 10.

Categories
Electrical Engineering

In this homework, you are going to design and implement an AES encryption core o

In this homework, you are going to design and implement an AES encryption core on your Xilinx FPGA board. Please follow PLD_Lecture on AES to figure out about AES algorithms. The block diagram of AES encryption core is shown in Figure 1.
Figure 1: AES Encryption Block.
In this assignment your AES core will be instantiated in your top module Verilog code. The input and output of your TOP module is based on Figure 2.
Figure 2: TOP Module.
Inputs:
● CLK100MHZ
It is the system frequency.
● SW[0] It is the reset of your project. You have the option to use it as the AES reset as well. When SW[0] is off it means your design is in reset state and when it is on, your design is in normal
operation. (this is a low active reset). In your board, we assume that if the switch is down, 2
it is considered as off, and it is on when the position of switch is up. (similar assumption is considered for all other switches)
● SW[1] This input is the starting command for the AES core. When the SW[1] is 1 the core should start to encrypt PLAIN_TEXT[127:0] based on the KEY[127:0]. Note that to start another 128-bit block encryption, SW[1] should get 0 and then get 1. You need to instantiate a filter for SW[1] (similar to previous homeworks) and then detect the rising edge of this starting signal (START input of your AES core). Accordingly, you can use the following codes; first instantiating the Filter module as below:
Then to detect the rising edge of SW_CMD, copy this code in your project:
Now SW_EDGE is the start of your AES core.
● SW[3:2] The output of your AES core, i.e., CIPHER_TEXT, is 128 bits. You should show this output on eight 7-SEG of your board. As you know, the 128 bit signal consists of 32 hex-digit. So, you do not have enough 7-SEG to show the output. Hence, when SW[3:2] is 0 the first 8 hex-digit is appeared on 7-SEG, and the second 8 hex-digit is shown when SW[3:2] is 1 and the third and fourth 8 hex-digit are shown when SW[3:2] is 2 and 3 respectively. To clarify, please consider this numerical example:
reg[127:0] CIPHER_TEXT;
CIPHER_TEXT = 128’h29C3505F571420F6402299B31A02D73A;
In Figure 3, you can see what should be shown on 7-SEGs for this example (the MSB bits are shown in the last row in this figure.)
Filter #(.wd(16), .n(65535), .bound(64000)) uut(.clk(CLK100MHZ)
,.data_in(SW[1]),.data_out(SW_CMD));
reg SW_CMD_back;
reg SW_EDGE;
always @(posedge CLK100MHZ)
begin
SW_CMD_back <= SW_CMD;
SW_EDGE RC[1] = 8’b00000001
Round 2 => RC[2] = 8’b00000010
Round 3 => RC[3] = 8’b00000100
Round 4 => RC[4] = 8’b00001000
Round 5 => RC[5] = 8’b00010000
Round 6 => RC[6] = 8’b00100000
Round 7 => RC[7] = 8’b01000000
Round 8 => RC[8] = 8’b10000000
Round 9 => RC[9] = 8’b00011011
Round 10 => RC[10] = 8’b00110110
In our example, the KEY is :
KEY [127:0] = 128’h5468617473206D79204B756E67204675;
32-bit LSB of KEY is 32’h67204675
byte 0 => 67
byte 1 => 20
byte 2 => 46
9
byte 3 => 75
byte 0 => s_byte => 85
byte 1 => s_byte => b7
byte 2 => s_byte => 5a
byte 3 => s_byte => 9d
g0 => b7 ^ 01 => b6
g1 => 5a
g2 => 9d
g3 => 85
g => 32’hb65a9d85
After calculating g, we should calculate the KEY for the next round. In Figure 9 the structure to
generate the next round key is presented. Note that KEY for each round is generated based on the previous round KEY.
Figure 9: KEY_GENERATOR.
KEY[127:96] => 32’h54686174
KEY[95:64] => 32’h73206D79
KEY[63:32] => 32’h204B756E
KEY[31:0] => 32’h67204675
KEY is Key of round 0 and KEY_1 includes the value of the first round key.
KEY_1[127:96] => KEY[127:96] ^ g = 54686174 ^ b65a9d85 = E232FCF1
KEY_1[95:64] => KEY[95:64] ^ KEY_1[127:96] = 73206D79 ^ E232FCF1 = 91129188 KEY_1[63:32] => KEY[63:32] ^ KEY_1[95:64] = 204B756E ^ 91129188 = B159E4E6 KEY_1[31:0] => KEY[31:0] ^ KEY_1[63:32] = 67204675 ^ B159E4E6 = D679A293
KEY_1[127:0] = 128’hE232FCF191129188B159E4E6D679A293
R0_S_mat_shift[127:0] = 128’hba75f47a84a48d32e88d060e1b407d5d
Round_1 = KEY_1 ^ R0_S_mat_shift = 128’h5847088B15B61CBA59D4E2E8CD39DFCE;
10
e2 91 b1 d6
32 12 59 79
fc 91 e4 a2
f1 88 e6 93
XOR
ba 84 e8 1b
75 a4 8d 40
f4 8d 06 7d
7a 32 0e 5d
=
58 15 59 cd
47 b6 d4 39
08 1c e2 df
8b ba e8 ce
KEY_1 After MIX_COLUMN Round1
Figure 10: data after round1.
So, if you are able to finish these steps (1-5), the thing that you need is to make a loop in your code to repeat steps 2-5 nine times. After that you have finished 9 rounds, the round 10 is the same as previous steps but the only difference is that you should exclude the MIX_COLUMN module in the round 10.

Categories
Electrical Engineering

read the “OpAmp design guidelines” first and use the given information “ECE433 p

read the “OpAmp design guidelines” first and use the given information “ECE433 project” it given C2 and ft to help calculation on “OpAmp design guidelines”. so I Chose a “good” value for Cc=3.4pf and the SR=10v/us. you need to calculate the rest question of “OpAmp design guidelines” you can use the file” new folder” to help you to do a part of the calculation of the “OpAmp design guidelines” . after that you need to run two-stage CMOS on the LTSPICE by applying your result calculation of the “OpAmp design guidelines”. I also attached the CMOS2 stage similarly with the project. you can use apart of it but you need to add the Q6,Q7 and (Q8 to Q12) with it
what you need to submit:
your calculation of “OpAmp design guidelines”
run two circuits ( circuit1 Q8 to Q12) (circuit2 Q1 to Q8) on the LTSPICE and apply what your calculation of “OpAmp design guidelines”
please ask as much as you can. i am willing to work together

Categories
Electrical Engineering

is connected to a 60Hz source, The impedance of the wire connecting it to the s

is connected to a 60Hz source, The impedance of the wire connecting it to the source is 0.48 + j0.64
The real power supplied by the source is ____ W?
10611
49605
15772
none
The reactive power supplied to the load is ____ VAR (2 decimals)
The apparent power supplied to the load is ____ VAR (2 decimals)
The power factor angle is ____ degrees (2 decimals)

Categories
Electrical Engineering

Part1: Online design for Current to Voltage converter with the mathematical equa

Part1:
Online design for Current to Voltage converter with the mathematical equations 4mA to 20mA converted to 1V to 5V.
Part 2:
Discuss 2 measurement methods for etch Indirect methods of Flow measurement and Electrical type Level measurement and Density measuremen.
Harvard referencing must be used

Categories
Electrical Engineering

Part1: Online design for Current to Voltage converter with the mathematical equa

Part1:
Online design for Current to Voltage converter with the mathematical equations 4mA to 20mA converted to 1V to 5V.
Part 2:
Discuss 2 measurement methods for etch Indirect methods of Flow measurement and Electrical type Level measurement and Density measuremen.
Harvard referencing must be used

Categories
Electrical Engineering

Write a short report about how the shift left and Universal Shift Register work.

Write a short report about how the shift left and Universal Shift Register work. Submit the
following via canvas:
▪ A pdf of your report (3 pages maximum: Diagram, basic idea, a flow chart, etc.)
▪ A 3-5 minutes ONLY video recordings explaining them in your own words. I need you to
explain the basic idea and the function in a very short and concise way

Categories
Electrical Engineering

Write a short report about how the shift left and Universal Shift Register work.

Write a short report about how the shift left and Universal Shift Register work. Submit the
following via canvas:
▪ A pdf of your report (3 pages maximum: Diagram, basic idea, a flow chart, etc.)
▪ A 3-5 minutes ONLY video recordings explaining them in your own words. I need you to explain the basic idea and the function in a very short and concise way